This invention relates to an integrator circuit comprising an input for receiving an input signal in the form of a sampled analog current, an output at which, in operation, the integrated input signal is made available in the form of a sampled analog current, a first current memory cell having an input connected to the input of the integrator circuit and an output connected to the input of a second current memory cell, the second current memory cell having a first output connected to the input of the first current memory cell and a second output connected to the output of the integrator circuit.
Such an integrator circuit has been disclosed in a paper by J. B. Hughes, N. C. Bird, and I. C. MacBeth entitled "Analog sampled-dated signal processing for VLSI using switched currents" presented at the IEE Colloquim on Current-Mode Analog Circuits on 17th Feb. 1989.
The integrator circuit disclosed in the paper depends on the matching between transistors to define the feedback current from the second to the first current memory cell. When producing ideal, i.e. lossless, integrators there is the possibility of the circuit becoming unstable if the loop gain becomes greater than one, that is if the matching errors are such that the feedback signal steadily increases. Similarly, when high Q circuits are required the integrator response becomes very sensitive to errors in transistor matching.